1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device primarily used in a high frequency band 800 MHz or higher.
2. Background Art
FIG. 21 is a plan view of a conventional high-frequency high-power internally matched type FET (Field Effect Transistor) designed to operate primarily at a frequency of 0.8 GHz or higher with an output power of 10 W or more.
Referring to the figure, the drain electrodes (not shown) of an FET 121 are connected to a matching circuit substrate 123 by wires 122. Further, the source electrodes (not shown) of the FET 121 are connected to the ground electrode (not shown) on the back surface through via holes (not shown) provided in the FET 121. Though not shown in FIG. 21, the gate electrodes (not shown) of the FET 121, like the drain electrodes, are connected to another matching circuit substrate (not shown). The matching circuit substrate 123, to which the drain electrodes are connected, is connected to an external matching circuit substrate 125 by wires 124. The width W7 of the FET 121 and the matching circuit substrate 123 is approximately 4 mm.
Generally, in an internally matched type FET, the impedance of the FET element must be converted to a high impedance 50 O or so. Therefore, the internally matched type FET must include an impedance converting line having a length corresponding to approximately λ/4, where λ is the operational wavelength of the semiconductor device determined by its operational frequency.
For example, referring to FIG. 21, when the relative permittivity and the thickness of the matching circuit substrate 123 are 90 and 380 μm, respectively, the length L7 of the matching circuit substrate 123 is set to approximately 2 mm at an operational frequency of 5 GHz. It should be noted that an external matching circuit substrate 125 may need to be added, as shown in FIG. 21, if the matching circuit substrate 123 alone cannot provide a desired impedance.
Incidentally, the FET 121 actually includes a number of FET elements 126 disposed in parallel to one another to achieve high output power. The number of FET elements 126 to be employed is determined based on the required output power. Usually, the FET 121 includes approximately 10 to 100 FET elements 126. Therefore, due to this configuration, loops may be formed between these FET elements 126, which might lead to parasitic oscillation. To prevent this from happening, substrate dividing slits 127 may be cut into the matching circuit substrate 123 to separate the strip conductors or wires, not shown, on the matching circuit substrate 123. Further, resistances 128 may be provided between the separated strip conductors as necessary to suppress odd modes.
The FET elements 126 are spaced only 5 μm to 100 μm apart from one another to achieve high power density. Therefore, to provide sufficient impedance conversion using the limited width (W7) of the FET 121, the substrate 123 is formed of a material that allows for formation of low impedance lines, that is, formed of a high dielectric constant material having a relative permittivity of approximately 30 to 300.
The impedance at the fundamental wavelength is designed based on a λ/4 impedance conversion circuit. Further, to achieve a high efficiency operation, it is necessary to optimize the impedance at the harmonics. Specifically, the Class-F operation requires even harmonics, such as the second harmonic, to be short circuited, while the inverse Class-F operation requires odd harmonics such as the third harmonic to be short circuited. (See, e.g., Akira Inoue et al., “Analysis of Class-F and Inverse Class-F Amplifiers”, TECHNICAL REPORT OF IEICE ED2000-231, p. 29-35, by The Institute of Electronics, Information and Communication Engineers.)
However, conventional internally matched type FETs are packaged such that the FET elements and one or more matching circuit substrates are disposed in parallel, restricting the space in the device width direction. This makes it difficult to add a new circuit (a stub, etc.) for matching at harmonics. As a result, these FETs cannot have optimized matching characteristics at harmonics, failing to achieve increased efficiency.
Further, they cannot sufficiently reflect harmonics internally within the matching circuit substrate, requiring a filter for preventing the leakage of the harmonics from the devices. This results in increased device cost and size.